Lateral bipolar transistors, in general, comprise three separate semiconductive regions of alternating conductivity types, such as n-p-n or p-n-p, extending along a common surface of a semiconductor substrate so that all of the electrical contacts to the various regions are at the same surface of the substrate. Such lateral bipolar transistors have many applications, particularly in integrated circuits. Bipolar transistors were generally used in analog circuits whereas MOS transistors were generally used in digital circuits. However, there have been circuits developed which require both MOS transistors and bipolar transistors in a single circuit and on a single substrate. These circuits are generally known as BICMOS circuits. To make such BICMOS circuits, it is necessary to have a fabrication process by which both MOS transistors and bipolar transistors can be formed during a common process sequence.
One type of lateral bipolar transistor is shown and described in the article of S.P. Gaur et al., entitled "Optimum Lateral PNP Transistor," published in IBM Technical Disclosure Bulletin, Vol. 26, NO. 9, Feb. 1984, pages 4584 and 4585. However, the lateral bipolar transistor described in this article has a number of problems. It includes a double layer polycrystalline silicon contact system with the first level making contact to the base and the collector and the second level making contact to the emitter. This double level system makes the surface topography thicker so that the photolithograhic process used to form the contacts becomes less accurate. Also, the double level system is not compatible with normal MOS processing so that it would be difficult to make this lateral bipolar transistor in a BICMOS device. Also, this lateral bipolar transistor uses a sidewall spacer to define the spacing across the base region between the emitter region and the surrounding collector region. In forming a sidewall spacer, the thickness of such a sidewall spacer can be changed only a very little amount and its width along the surface of the base region is limited. Therefore, the spacing between the emitter region and the collector region can be varied only a little. Since this spacing controls the beta of the transistor, the beta of this type of lateral bipolar transistor can be varied only over a narrow range and has a maximum value. Thus, the lateral bipolar transistor disclosed in this article is not suitable for use in making some BICMOS integrated circuits and can form transistors having only a limited variation in beta.
Processes have been developed for making BICMOS integrated circuits which include a bipolar transistor disclosed in U.S. Pat. No. 4,808,548 to M. Thomas et al., issued Feb. 28, 1989, and entitled "Method of Making Bipolar and MOS Devices on Same Integrated Circuit Substrate" and in U.S. Pat. No. 4,824,796 to Tzu-Yin Chiu et al., issued Apr. 25, 1989, and entitled "Process for Manufacturing Semiconductor BICMOS Device." However, in the BICMOS circuits of each of these patents the bipolar transistor is a vertical bipolar transistor and not a lateral bipolar transistor.
Therefore, it is desirable to have a method for making bipolar transistors which is compatible with a method for making MOS transistors so as to permit forming BICMOS integrated circuits.